NOVEL QUAD PARALLELIZED ARCHITECTURE FOR DIGITAL IMAGE PROCESSING CONVOLUTION ON FPGAs

The Digital Image Processing convolution is core block for Convolution Neural Networks (CNN) which is used in Deep CNNs and is used for advanced applications of feature extraction, image recognition etc. This paper introduces 2 novel hardware architectures for convolution process one of them is hardware Quad parallelized architecture. Performance comparison is done and I proved that parallelization is highly useful. This parallel one can speed up the process of convolution filtered image data transmission through telemedicine communication network etc. Implementation is done for 64 by 64 size matrix, 3 by 3 Kernel using Xilinx Vivado 2015.2 tool on Xilinx Artix-7 FPGAs using Verilog HDL.