Effective and Efficient Optimization in RC4 Stream

At present technology, power saving technique is one of the important criteria while designing a hardware for RC4 stream cipher. So this paper proposes a BCD to Excess- 3- adder to build an efficient hardware with parallel processing system for low power consumption without compromising the speed and security in cryptography. Loop unrolling and Pipeline concepts are used for expeditious hardware implementation. This design is realized on XC3S100E FPGA with VHDL language.