Design of Area Efficient Low Power CMOS Adder Cell

In this paper, by combining XOR/XNOR-based logic and pass-transistor logic with conventional PMOS/NMOS network, a new structure of full adder has been proposed. The evolution of the proposed adder cell from Low Power (LP) XOR/XNOR based SUM to Gate Diffusion Input (GDI) XOR/XNOR based SUM and CARRY with reduced transistor count have been described. Comparisons between the proposed full adder with adders designed by other existing logic styles and their counterparts have been done. The proposed adder outperforms the other full adders, particularly in terms of power consumption, power delay product (PDP) and area.