DESIGNING RESOURCEFUL COUNTER FOR FIFO?

First-in first-out memories (FIFOs) have progressed from objectively simple logic functions to highspeed buffers combining large blocks of SRAM. FIFOs are often used to carefully pass data from one clock dominion to another asynchronous clock dominion. Using a FIFO to pass data from one clock domain to another clock domain requires multi- asynchronous clock design techniques. This concept will detail one method that is used to design, synthesize and analyze a safe FIFO between different clock domains using Memory counter that are synchronized into a different clock domain before testing for "FIFO full" or "FIFO empty" conditions. The fully analysed, synthesized counter can be included in FIFO.