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Journal: International Journal of Computer Science and Mobile Computing - IJCSMC (Vol.3, No. 10)

Publication Date:

Authors : ; ;

Page : 304-310

Keywords : Cache; Low power; LSQ Tag array and TLB;

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This paper presents a new cache design technique, referred to as early tag access (ETA) cache, to improve the energy efficiency of data caches in embedded processors, to determine the destination ways of memory instructions before the actual cache accesses. It, thus, enables only the destination way to be accessed if a hit occurs during the ETA. The new ETA cache can be configured under two operation modes to exploit the tradeoffs between energy efficiency and performance. It is shown that our technology is very effective in reducing the number of ways accessed during cache accesses. The ETA cache achieves over 52.8% energy reduction on average in the L1 data cache and translation look aside buffer. It is more effective in energy reduction while maintaining better performance and this technique is used to other levels of cache hierarchy and deals with multi threaded workloads.

Last modified: 2014-10-17 19:43:35