HARDWARE ACCELERATOR FOR SQUAREDEUCLIDEAN DISTANCE

With an increased reliance on the integrated circuits (IC), there has been a tremendous increase in the demand for the intellectual property (IP) cores by the industries, as they showcase minimal design time and high productivity. This paper delineates a novel pipelined architecture of Euclidean Distance IP core and Squared Euclidean Distance IP core, designed to work on IEEE 754–Floating-point SinglePrecision Data format, with the flexibility to select a number of variables (data points) up to 65535. IP Core is designed and implemented on FPGA-Zedboard Zynq-7000, and to be used in future on FPGAs.