A NOVEL APPROACH FOR POWER OPTIMIZATION IN SEQUENTIAL CIRCUITS USING LATCH BASED CLOCK GATING

Low power design methodologies have gained more prominence in the present designs. Designers will have to come up with amicable designs in order to reduce the power. In synchronous circuits, clock is distributed to all the blocks and it consumes more power dynamically. Clock gating is a technique in which the gating signal has the potential to enable or disable the clock signal. In this paper clock gating macro is inferred in pre-mapping stage of synthesis. Latch based clock gating is chosen as it reduces the glitches in the circuit. The synthesized netlist is functionally verified with RTL netlist and synthesized netlist, which is followed by PnR. Then power is calculated using test vectors generated after functional verification. Synthesis is carried out for enable signal driven by combinational logic, shift register, counter and sequence detector. Implementation is done to check different scenarios of enable signal and to vary the number of flip-flops used. The dynamic power consumption has reduced by 0.284mW in FSM, 11.754mW in 200-bit counter and 13.441mW 200-bit enable signal driven by combinational logic.