DESIGN AND DEVELOPMENT OF 4-BYTE SRAM ARCHITECTURE

In VLSI, there is integration of hundreds and thousands of transistors to form a chip (or) microchip. SRAM is utilized for computer cache memory and a chunk of random access memory digital to analog converter on a video card. SRAM keeps data constant, without the need of memory module to be refreshed periodically. SRAM takes main role in very large scale integrated circuit (VLSI) due to its storage capacity and small access time. In this work the simulation study of different SRAM cells 4+2T SRAM, 4TSRAM, 5T SRAM and 6T SRAM are done. Also a 4byte SRAM architecture with row decoder, column decoder, SRAM cell, pre-charge circuit, sense amplifier and write driver circuit are simulated using EDA tool in 45nm technology. The average power delay and area various SRAMs are calculated and compared. SRAM5T is showing better results for Average power consumption and delay while SRAM4T is better in terms area.