LOW AREA FPGA IMPLEMENTATION OF FIR FILTER WITH OPTIMAL DESIGNS USING PARKS-MCCLELLAN

Finite Impulse Response (FIR) filter is enormously used in digital signal processing applications because of its different features such as Bounded-Input-Bounded-Output (BIBO) stability, phase linearity and easy implementation for high order filters with many multipliers. The increment in multipliers leads to increase hardware complexity and power of the FIR filter. Thereby, designing a FIR filter by satisfying all the design constraints plays a vital role in DSP applications. In this research, an important type of FIR filter namely Interpolated Spectral Parameter Approximation (ISPA) filter is proposed to minimize the hardware utilization. The integration of Carry Look ahead Adder (CLA) and Vedic Multiplier (VM) are used to minimize the amount of logical elements in the ISPA filter. Moreover, the delay of the ISPA filter is minimized by increasing the operating frequency of the ISPA filter. The coefficient will be generated using Parks-McClellan algorithm. The Modelsim 10.5 and Xilinx 14.7 are used to implement the ISPA filter along with optimal adder and multiplier. The performances of the ISPA- PM-FIR filter are analyzed in terms of filter output, LUT, flip flops, slices, power and delay. An improvement of about 6% hardware utilization and 0.0057ns fractional delay has been obtained than the existing techniques and makes it suitable for designing an efficient FIR filter for VLSI and DSP applications.