DESIGN OF FIR FILTER ALGORITHM FOR NOISE REMOVAL IN ECG SIGNAL USING OPEN CORE SoC

The emerging technology in computer architecture has led to the development of various ISAs depending on the needs of the desired technology, architectures, and processor cores. Instruction Set Architectures (ISAs) for processors from Intel, AMD, Intel, RISC-V, etc. This has provided the path to implement various functions on an open core SoC Platform. Among the many DSP applications, the FIR filter has been implemented on an open core SoC platform that uses RISCV. Here specifically filtering of noise from ECG signal. The performance cycle count has been obtained for the same and compared with its counterpart ARM M7 on the Keil platform.