Importance of Capacitor-Less DRAM and its Scaling Perspectives

In this paper, we analyze the need for a Capacitor-less DRAM and explore the physics behind the operation modes and the scaling limits of double-gate (DG) 1T-DRAM cells. We find that this configuration allows infinitely long retention of state 1, whereas the total retention time of state 0 is limited by band-to-band tunneling (BTBT) at the source-bulk or drain-bulk junctions. Extensive and careful scaling analysis shows that short-channel effects caused by the lowering of barrier between source/drain to bulk limits longitudinal scaling, whereas BTBT limits transverse scaling. We realize that the choice of the right geometry (L, W, tox), involves a tradeoff between current amplitudes and READ sensitivity. This paper also highlights a novel Capacitor-less Double Gate Quantum Well Single Transistor DRAM approach for even better scalability and retention time. Therefore, the introduction of a storage pocket for holes and the engineering of the spatial distribution of holes significantly improves cell performance. A few other unconventional Capacitor-less DRAMs are also stated.