Survey of Efficient NOC Router Designs and Programming Model for Embedded Application

System on chips containing IP cores and traditional methods for communication such as bus, are not suitable solution for future System on chips (SOC). As the complexity of the SOC is increasing, it is impossible to send signals from one end to another end within a clock cycle. Problems such as global wire delay and global synchronization will be the limitations, Network on chip is an emerging approach for the implementation of on chip communication architecture. Network on chip a communication centric approach and it is a possible solution for communication architecture of future System on chips that are composed of switches and IP cores where communicate among each other through switches. . In contrast to normal beliefs, on chip interconnections suffer from certain physical limitations which lead to great performance reduction. How the changes made in traditional NOC to best fit for the today�s requirement is the subject of this paper. We discuss new techniques. We discuss the unique problems posed by synchronous NOCs and discuss the different Asynchronous NOC model as the promising solution. We survey work to build accurate simulation models for on chip communication, propose a programming model for efficient router design for embedded application.