A Noble Research on to Reduce Clock Power by Using Multi Bit Flip FlopsJournal: Iord journal of science & technology (Vol.01, No. 05)
Publication Date: 2014-7-10
Authors : Sonawane Dipak Ganesh; Asst.Prof.Ashish Panchal; Prof.Sharad Jain;
Page : 01-07
Keywords : Index Term? logic; ternary; arithmetic circuits; flip flops.;
Abstract? Power reduction has become a vital design goal for sophisticated design applications for VLSI design system. The need for low power has causes a major paradigm shift in which power dissipation is as important as performance and area. Multi-bit flip-flop is an effective power-saving implementation methodology by merging single-bit flipflops in the design. The multi-bit flip-flops can reduce clock dynamic power and the total flip-flop area effectively. The multi bit flip-flop technique is one of the techniques used to reduce the clock power. The power reduction is achieved through the merging of flip-flops based on certain timing constraints. This paper a survey for identifying the Power Reduction by Using Multi-Bit Flip-Flops based on various technical papers available in the public domain. Index Term? logic ,ternary ,arithmetic circuits, flip flops.
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