Towards New Error Detection Circuits Using QCA

Quantum-dot cellular automata nanotechnology has achieved world-wide attention for their prominent features such as low power consumption, small size and fast switching speed as compared to the conventional CMOS transistors. Reliable data transmission over telecommunication network systems is an increasing demand at nano-scale. Several QCA based nano-devices have been implemented to detect errors during data transmission. In this paper, an efficient even parity generator and checker has been proposed using QCA. The simplest and effective technique used to detect errors in the message word. An optimal number of QCA cells have been used for the design and implementation of the parity logic circuits. A detailed performance evaluation analysis is performed in different aspects to authenticate the proposed bit preservation circuits has superb performance in comparison to previously reported works. The functionality and simulation results of the proposed circuits have been verified using QCADesigner tool Ver.2.0.3.