ResearchBib Share Your Research, Maximize Your Social Impacts
Sign for Notice Everyday Sign up >> Login

Low Power and High Speed Design Of FIR Filter

Journal: Iord journal of science & technology (Vol.01, No. 05)

Publication Date:

Authors : ; ;

Page : 25-32

Keywords : Index Terms: Xilinx ISE; FIR; VHDL.;

Source : Downloadexternal Find it from : Google Scholarexternal


Abstract- Finite impulse response (FIR) filters are widely used in various DSP applications. The low-power or high speed techniques developed specifically for digital filters can be found in. Most of the applications in digital communication, seismic signal processing (noise elimination), speech processing (adaptive noise cancelation), and many other synthesis operations of signal require large order FIR filters ,since the number of multiply-accumulate (MAC) operations required per filter output increases linearly with the filter order, therefore implementation of these filters of large orders is a challenging task .In this paper, we propose designing of FIR filter using high speed low-power multiplier adopting the new implementing approach. We are using Vedic Multiplier. Vedic Multiplier is a fast processing multiplier as number of partial products are less. The carry look ahead adder will avoid the unwanted addition and thus minimize the switching power dissipation. The architecture is coded in VHDL, simulated in ModelSim and synthesize in Xlinx ISE Software .

Last modified: 2015-01-13 15:41:20