Analysis, Physical Design and Power Optimization Of Block Signal Estimator for Hign Speed Serial InterfaceJournal: International Journal of Science and Research (IJSR) (Vol.6, No. 8)
Publication Date: 2017-08-05
Authors : Sachin Revannavar; H. V. Ravish Aradhya;
Page : 916-920
Keywords : floorplan; placement; CTS; routing; sign off timing and physical verification;
Present day in VLSI world, the way the complexity level of IC technology is advancing day by day, it is very important to have best design methods and power optimization schemes for the PD (Physical Design) along with timing closure and physical verification. Todays complex IC designs require good physical design strategies to ensure its high quality and also to meet the required timing target. There are different methodologies that can be used when designing but the paper concentrates on the Top down based approach. Traditionally Blocks are tested from the top level which was giving low coverage due to lack of flexibility. And also there is a chance of missing some freedom to floor plan the design at the block level.
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