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Design and Simulation of a Multiport Memory Controller for Communication between Master and Slave Port

Journal: International Journal of Science and Research (IJSR) (Vol.6, No. 8)

Publication Date:

Authors : ; ; ;

Page : 1086-1089

Keywords : Altera Quartus II; Buffers; DDR3 SDRAM; Flexible communication; Modelsim 66a;

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The dynamic memory controller plays an important role in system-on-a-chip (SoC) designs to provide enough memory bandwidth through external memory for DSP and multi-media processing. As the multimedia applications are growing rapidly past a decade. The applications of multi-media for processing high resolution video, data and audio sequences are known to require a high speed and high-density memory port. The memory is required for data storage in real time applications, the memory controllers support DDR3/DDR2/DDR/SDRAM memories and it can be configured according to their requirements. In spite much research on performance improvement, the external memory performance is lagging. Hence the memory controller is essential. The proposed architecture of multiport memory controller is designed for flexible communication between the master and the slave ports and also the communication speed is increased as the design contains a number of buffers for, and also embedded memory for configuration storage and an arbiter including round robin scheduling scheme for scheduling the read/write accesses. The design technique provides flexible systems and independent from other system architecture. The design is modelled in Altera and the read/write simulation results are acquired in Modelsim 6.6a using an external DDR3 SDRAM memory.

Last modified: 2021-06-30 19:52:24