ResearchBib Share Your Research, Maximize Your Social Impacts
Sign for Notice Everyday Sign up >> Login

FPGA Implementation of LDPC Encoder and Decoder using Bit Flipping Algorithm

Journal: International Journal of Science and Research (IJSR) (Vol.3, No. 5)

Publication Date:

Authors : ; ;

Page : 1683-1690

Keywords : HDL; Error Correction Codes; ISE; AWGN;

Source : Downloadexternal Find it from : Google Scholarexternal


Communication system transmits data from source to transmitter through a channel or medium such as wired or wireless. The efficiency of received data depends on medium and noise. LDPC codes are used to correct the errors by adding redundant symbols to the original data called as Error Correction Codes (ECCs). Without ECCs data need to retransmit if it could detect there is an error in the received data. ECC are also called as forward error correction (FEC) as we can correct bits without retransmission. ECCs are really helpful for high speed and long distance Communication LDPC consist of mainly Encoder and Decoder blocks, AWGN channel, Detector. These blocks are designed by using Verilog HDL with Xilinx ISE Design suite 12.4 version tool. The designs implemented in Xilinx SPARTAN 3E XC3S500EFG320 FPGA board.

Last modified: 2021-06-30 19:59:36