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Low Power 8 bit Analog to Digital Converter (ADC) in 180 nm CMOS Technology

Journal: International Journal of Science and Research (IJSR) (Vol.2, No. 7)

Publication Date:

Authors : ; ;

Page : 417-418

Keywords : Cadence; �CMOS; DAC; Sampling rate; VLSI;

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Analog to Digital Converter (ADC) is developed for operating at ultra low supply votages. Circuit is realized in 180 nm CMOS technology. The pre-simulation of ADC has been achieved on Caadence Virtuoso. The purpose of this work to develope a biomedical application. The research is focused on the design of ADC with sampling rate 100KS/s. It has very low cost and high speed technology with relative medium resolution and accuracy. This implies it posseses a good trade off between speed and cost. R2R DAC is used with a different approch in which matching of resistors is more easier than a conventional ADC.

Last modified: 2021-06-30 20:19:44