Design and Analysis of CMOS Multipliers at 180nm and 350nmJournal: International Journal of Science and Research (IJSR) (Vol.3, No. 9)
Publication Date: 2014-09-05
Authors : Jagmeet Singh; Hardeep Singh;
Page : 943-949
Keywords : Array Multipliers; Full adder; CMOS; CPL; DPL;
Due to rapid growth of portable electronic systems like laptop, calculator, mobile etc. and the low power devices have become very important in today world. Multiplier is the important arithmetic unit in Microprocessors and DSPs and also has a major source of power dissipation. To reduce the power dissipation is the important key to satisfy the power budget of various circuits. This paper elaborates the array multiplier and tree multiplier through different logic styles. In this the fundamental units to design a multiplier are adders. The various types of adders used in this paper are Complimentary Pass transistor Logic (CPL), Double Pass transistor Logic (DPL) and Conventional Static CMOS (CSL) Logic design styles using the 350nm and 180nm technologies at different supply voltages. The main objective of our work is to analysis the CMOS Multipliers in terms of Propagation delay and Power dissipation and Transistor count of 4x4 multipliers. The design of full adder for low power is obtained and the low power units are implemented on the array multiplier and tree multiplier and the results are analyzed for better performance. The designs are done with the help of TANNER S-EDIT tool and are simulated using T-SPICE.
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