Implementation and Comparison of Tree Multiplier using Different Circuit Techniques

Multiplication is an important fundamental function in arithmetic operations and is used in various applications. Tree multiplier is a high speed parallel multiplier used for large size operands. In this paper 4x4 Tree multiplier is implemented with CMOS logic, CPL logic and DPL logic technique and various performance parameters such as power, delay and transistor count of Tree Multiplier using different circuit techniques are discussed and compared. Different types of circuit techniques have a unique pattern of structure to improve their performance in various means like low power, minimal delay and decreased PDP. All the circuits are designed and simulated using 90nm technology, 2.5V supply Also layouts of all the basic circuits (AND2 and Full Adder) using CMOS logic, CPL logic and DPL logic are designed and the layout of the Tree multiplier using CMOS logic is designed and verified by its corresponding waveform.