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An Efficient Performance Analysis of Different Adder Topologies?

Journal: International Journal of Computer Science and Mobile Computing - IJCSMC (Vol.4, No. 1)

Publication Date:

Authors : ; ; ;

Page : 284-290

Keywords : carry look ahead adder; carry select adder; modified carry select adder; propagation delay; Synthesis; Simulation;

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This survey deals with the study of the comparative analysis of the performance of different adder logics. Here for our analysis we have considered the performance of four different adders such as carry look-ahead adder (CLAA), carry select adder (CSLA), Modified Carry select adder and carry save adder. The above design of multiplier multiplies two 16-bit unsigned integer values and gives a product term of 32-bit values. These multipliers have been designed in Verilog, simulated on Modelsim and synthesized on Xilinx FPGA Spartan 3E xc3s500E and their area; power and delay are calculated and compared.

Last modified: 2015-01-24 18:01:04