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Fault Tolerant Linear State Machine Design Approach for Safety Critical Systems Implemented on FPGA

Journal: International Journal of Science and Research (IJSR) (Vol.4, No. 2)

Publication Date:

Authors : ; ;

Page : 1635-1636

Keywords : TMR tripple modular redundancy; Voter logic;

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In this paper, a new method for the design of fault tolerant linear state machines with initial state 0 and one dimensional input and one-dimensional output is proposed. It is shown that the LFSR-implementation of the transfer function of a linear automaton can be utilized to correct transient errors in the memory elements. Since the state vector of a linear automaton is uniquely determined by the last n inputs and outputs, a transient error in a memory element can be corrected within n clock cycles by use of the corrected output symbols, where n is the number of components of the state vector

Last modified: 2021-06-30 21:22:46