Approximate Compressors for 32 X 32 Bit Multiprecision MultipliersJournal: International Journal of Science and Research (IJSR) (Vol.4, No. 2)
Publication Date: 2015-02-05
Authors : Sunanda Balan; Chithra M.;
Page : 1751-1754
Keywords : FWM; MPM; Xilinx ISE design suite 81 and Modelsim 63;
Consumers demand for increasingly portable, high performance multimedia and communication products. This forces strict constraints on the power consumption of individual internal components. Most of the internal components of DSP are multipliers. Embedded application become essential to design more power aware multipliers. The basic building block of the multipliers can be used either in two ways. First it can be used as independent smaller precision multipliers else it can be used as work in parallel to perform high precision multipliers. Low power consumption and smaller area are some of the most important criteria for the fabrication of DSP systems and high performance systems. Optimizing the speed and area of the multiplier is a major design issue. However, area and speed are usually conflicting constraints so that improving speed results mostly in larger areas. Various types of multiplications such as fixed length multiplication and multiprecision multipliers with 3 sub-block and 4 sub-block multipliers is to enhance power and area. Booth radix4 Wallace tree adder algorithm is used in the 32X32 bit fixed width multiplier and multiprecision multipliers with 4 sub-blocks and 3 sub-blocks. Silicon area is optimized by applying operation reduction techniques that replaces a multiplier by adders/subtractors. Synthesis can be done by means of Xilinx ISE design suite 8.1 and Modelsim can be used for simulation.
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