FPGA Based Architecture for High Performance SRAM Based TCAM for Search Operations

Ternary Content Addressable memory is a type of memory that allows the memory to be searched by content rather than by address. It performs high speed look-up operations within a single clock cycle. But when compared to RAM technology the conventional TCAM circuitry has certain limitations such as low access time, low storage capacity, circuit complexity and high cost. So we can use the benefits of SRAM by configuring it to behave like TCAM. The project focuses on a memory architecture based on the hybrid partitioning concept which emulates the TCAM (Ternary Content Addressable Memory) functionality with SRAM. The hybrid partitioned SRAM based TCAM logically dissects conventional TCAM table in a hybrid way (row-wise and column-wise) into TCAM sub tables, which are then processed to map on their corresponding memory units and match address is produced. The 64*32 hybrid partitioned SRAM based TCAM can be implemented in Xilinx Spartan 3E. The SRAM based TCAMs offers better search performance and scalability. So the SRAM based TCAM can be used in networking applications such as packet switching and packet classification in ATM communication systems.