A High Quality Image Scaling Processor With Reduced Memory

The digital images can be resized and the process of doing it is called as image scaling. The applications such as sharpening of the image, image zooming, processing edge structures in an image etc, uses image scaling as one of its important method. Image scaling is a computationally expensive operation. High memory requirement and computation complexity are characteristics of most of the high quality image scaling algorithms. For very large scale integration (VLSI) implementation, low complexity and low memory requirement image scaling algorithms are necessary. Here, the image scaling algorithm consists of sharpening spatial filter, clamp filter and simplified bilinear interpolation. The sharpening spatial filter and clamp filter serves as pre-filters prior to bilinear interpolation operation. These filters are combined into a combined filter by the 2D convolution of T- model or inverse T- model convolution kernels that represent them. The filter combining technique reduces computation resources and memory buffer. Hardware sharing techniques are used to reduce the computational complexity and computing resource needed. Bilinear interpolation is an image restoring algorithm. It is popularly used in VLSI implementation because of its low complexity and simple architecture. The architecture can be modeled in Verilog HDL, simulated using ModelSim XE III 6.3c and synthesized using Xilinx ISE design suite 8.2i and can be implemented in Spartan 3 FPGA.