Reed Solomon Decoder with Parallel Syndrome Computation on FPGA: A Review

-In wireless, satellite, and space communication systems, reducing error rate is critical. High bit error rates of the wireless communication system require employing various coding methods on the data transferred. Channel coding for error detection and correction helps the communication system designers to reduce the effects of a noisy transmission channel. The purpose of this paper is to study and investigate the performance of Reed-Solomon decoder that is used to decode the data stream in digital communication. In this paper, the proposed work is to implement the decoder of Reed-Solomon (RS) coding scheme on the platform of VHDL using algorithm. Implementation will be done on VLSI Hardware Description Language (VHDL) and results can be seen on Field Programmable Gate Array (FPGA). This paper reviews the Reed Solomon decoder performance over Xilinx package.