A Survey on Implementation of Random Number Generator in FPGA

A pseudo random number generator (PRNG), also known as a deterministic random bit generator (DRBG), is an algorithm for generating a sequence of random numbers. This paper presents an implementation of pseudo random number generator. The design has been specified in VHDL and is implemented on altera FPGA device. It is based on the Residue Number System (RNS), which gives us the way to design a very fast circuit. This paper presents design and implementation of a pseudo-random number generator based on Blum Blum Shub, XOR Shift, Fibonacci series and Galois LFSR methods. We will demonstrate that how the introduction of application specificity in the architecture can deliver huge performance in terms of area and speed. The design will specify in VHDL and will analyze on altera FPGA parameter. Which will give us higher throughput and also the parameter like area, propagation delay and power requirement.