Assertion-Based Formal Verification of CPU-Cache Crossbar of OpenSPARC T1 Processor

Functional verification of complex designs, such as multi-core processors, is a challenging task in the entire verification cycle, because bugs which are not uncovered during this phase will carry on to the later design stages. The cost of fixing bugs is very high at later stages as compared to fixing them at the RTL implementation phase. Conventional verification methods like coverage-driven simulation techniques may not be able to uncover all the bugs due to their inability to exercise corner-case scenarios in a design. Formal methods like theorem proving, assertion-based verification are exhaustive and detect all corner-case bugs. This paper proposes an assertion-based formal approach for the verification of the CPU-Cache Crossbar module of the SPARC T1 processor, whose behavior is characterized by complex request patterns originating from the multiple cores to access shared resources such as the Level 2 cache memory banks, floating-point unit, and I/O Bridge ideal candidates for an assertion based formal verification approach.