Design of Microprocessor Hardware Self-Test Unit on FPGA

The rapid advancement in the microelectronics design is making a significant demanding situation to design validation in general, but dealing with pipelined microprocessor is remarkable more challenging. The main concern for industry nowadays is testing processor cores embedded in system on chip (SOC). Software based self Test SBST and Built-In Self Test BIST are some of techniques as being developed dynamically and used in many VLSI chips including microprocessor. The proposed project mention a new technique which combines the SBST and BIST method which is done by insertion of programmable infrastructure IP named of Microprocessor Hardware Self-Test (MIHST) that is connected to the system bus. The merits of using the MIHST technique is it has same or higher defect coverage compare to SBST method, test execution time is reduced, Intellectual Property (IP) of the processor core is preserved, for the storing of the test program or the test data does not need the system memory. An experimental result clearly shows the feasibility and effectiveness of the approach which are evaluated on the pipelined processor and implemented on FPGA