Design and Implementation of Rijindael's Encryption and Decryption Algorithm using NIOS-II Processor

One of the foremost vital problems in communication customary is that the secure transport protocols. This paper can offer a doable resolution for Rijindaels encryption and decoding algorithmic program using NIOS II processor, provided by ALTERA to be enforced in FPGA. We are going to see the performance of Rijindaels AES using NIOS II/e (economic), NIOS II/s (standard) and NIOS II/f (fast). The suggested system is capable of encrypting and decrypting 128, 198 and 256 bits of data. The FPGA has the potential of data processing and hardware modification. The NIOS II is a versatile embedded processor family that represents high performance, lower overall cost, power consumption, complexity combining several functions into one chip. The look of the Rijindael algorithmic program supported NIOS II + FPGA are able to do a better processing speed whereas it occupies comparatively low resources. The inputs and the control of an AES algorithmic program is written in C language and is interfaced with the system using general purpose input and output (GPIO) and also the management part is enforced in software in NIOS II integrated development environment (IDE). The implementation is completed on Cyclone II FPGA kit. The results are analysed on the personnel computer (PC) in IDE console window.