Design of Wallace Tree Multiplier using Adiabatic Logic

Wallace Tree Multiplier (WTM) is one of the fastest multiplier used in many data-processing processors to perform fast arithmetic functions. From the structure of the RCWM (Reduced Complexity Wallace Tree Multiplier), it is clear that there is scope for reducing the area and power consumption. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the WTM. Conventional WALLACE TREE MULTIPLIER (WTM) is still area-consuming due to the CMOS switching structure. The excessive area overhead makes WTM relatively unattractive but this has been circumvented by the use of Adiabatic Logic introduced. The logic operations involved in conventional RCWM (Reduced Complexity Wallace Tree Multiplier) and Wallace Tree Multiplier (WTM) are analyzed to study the data dependence and to identify redundant logic operations. Reduced complexity Wallace multiplier (RCWM) reduced number of half adders used in Standard Wallace Multiplier (SWM) with a slight increase in full adders to reduce the number of gates. Adiabatic Logic eliminated all the redundant logic operations present in the conventional RCWM (Reduced Complexity Wallace Tree Multiplier). Experimental analysis shows that this architecture achieves the three folded advantages in terms of area and power.