A Low Power Array Multiplier Design using Modified Gate Diffusion Input (GDI)

This paper proposes a new low power and low area 4x4 array multiplier designed using modified Gate diffusion Input (GDI) technique. By using GDI cell, the transistor count is greatly reduced. Basic GDI technique shows a drawback of low voltage swing at output which prevents it for use in multiple stage circuits efficiently. We have used modified GDI technique which shows full swing output and hence can be used in multistage circuits. The whole design is made and simulated in 180nm UMC technology at a supply voltage of 1.8V using Cadence Virtuoso Environment.