Low Power 1 bit Adiabatic SRAM Cell Design

This paper presents the design of an Adiabatic static RAM with a bit line driver that reduces power dissipation by efficiently recovering energy from the bit capacitors in 180nm technology. Cadence simulations of a simple 1 bit Asymmetrical Adiabatic SRAM, that includes the energy recovering bit line drivers, and the sense amplifiers, show over 35 % of power savings at 1.8 V, in comparison with its conventional counterpart.