High performance Radix-4 FFT using Parallel Architecture

In this paper, we propose a design architecture of an efficient Radix-4 FFT algorithm using parallel architecture. This parallel architecture plays an important role in the FFT computation speed of data samples. The proposed algorithm has a better power and area consumption compared to the conventional Radix-4 FFT Algorithm. By the repeated use of twiddle factors, algorithm reduces the complexity and memory consumption in terms of hardware point of view.