Reduction of Static Power Dissipation in CMOS Inverter using Extra Nodes and Substrate Current

High performance VLSI circuit design can be done by miniaturization of device channel length to sub-100nm dimension. But it may result in significantly higher leakage current. The increase in leakage current leads to significant increase in its power dissipation. For the past few years, various methods and device structures are proposed to solve this issue. In this work, we have tried to reduce the static power dissipation by either raising source or falling drain voltage since both lead to a reduction in VDS. CMOS inverter while designed with our proposed technique shows voltage transfer characteristics comparable to the conventional CMOS inverter and results in large reduction in substrate current and thereby reducing static power dissipation.