Design for Low Power Multiplier Based On Fixed Width Replica Redundancy Block & Compressor Trees

This paper establishes designing multipliers that are of high-speed, low power, and regular in layout are of substantial research interest. Multiplier speed can be increased by reducing the generated partial products. Many attempts are done to reduce the number of partial products generated in a multiplication process. One of them is Wallace tree multiplier. Wallace Tree CSA structures are used to sum the partial products in reduced time. Speed can be increased by incorporating compressors with wallace tree technique. Therefore, minimizing the number of half adders used in a multiplier which will reduce the circuit complexity.