High Performance Hardware Realization of Advanced Encryption Standard

Advanced Encryption Standard (AES) is a cryptographic algorithm which has wide range of applications. Each application has different power, speed, and resource utilization requirement. This paper thoroughly analyses implementation strategies of Advanced Encryption Standard (AES) algorithm and proposes four different architectures for AES implementation, each of these architectures targeting different applications. Each operation in AES is mathematically analyzed and implemented separately. Based on implementation results best suited strategy of hardware implementation can be chosen for each of four architectures. For this architecture 1 has been proposed and analyzed One of the main contributions of this work is reordering and merging different operation of AES encryption so as to achieve higher speed and lesser device utilization for encryption hardware. Merging techniques have increased the hardware efficiency by 36 % compared to previous implementation. This work also suggests pyramid buffer hardware implementation approach to achieve higher throughput for decryption module. This work suggests very low power solution for AES encryption by merging and rolling the encryption architecture.