Detection of Soft Errors in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes

In modern scenario demands for nano-devices has been increased. But the problem with these devices is that they are more prone to soft errors, especially nano-memory devices. A fault secure memory system can be implemented by using majority logic decoder. This is beneficial because majority logic decoding can be implemented serially with simple hardware but decoding time is large, in memory application memory access time increases because of this. The suggested method checks whether a word under scrutiny has errors in the first three iteration of majority logic decoding and if there are no errors decoding ends without completing the rest of the iteration. Since most words in memory will be error free, the average decoding time is greatly reduced. In this paper this technique is applied to a class of Euclidean geometry low density parity check (EG-LDPC) codes that are one-step majority logic decodable. The results obtained shows that this technique can be applied in EG-LDPC effectctively.