Design and Performance Analysis of TFA Cell Using CNTFET

In this paper a clocked ternary full adder cell using Carbon nanotube field effect transistor (CNTFET) is proposed in which pull-up and pull-down networks are used along with a clock reset circuit and a MUX at the output. Ternary logic is preferred for the design over conventional binary logic as it helps to reduce circuit complexity and hence reduces chip area. The performance of proposed TFA cell is evaluated and compared with the reference design in terms of parameter such as power dissipation and delay.