Design of High Speed Flash Analog to Digital Converter Using Multiplexer and Comparator

A high speed Flash analog-to-digital converter (ADC) using mux based comparator to reduce the number of preamplifiers and comparators is introduced. A conventional N-bit flash ADC requires 2^N-1 preamplifiers and comparators while The high speed flash ADC only needs 2^ (N-3) +2 preamplifiers and 2^ (N-2) +1 comparators. For a 6-bit resolution, the high speed flash ADC requires a reduce number of preamplifiers and comparator, compare with those of the conventional flash ADC. The high speed flash 6-bit ADC consists of a reference ladder, a T/H circuit, 10 preamplifiers, 17 comparators, a (2x1) -MUX, 8 (4x1) -MUXs and logic gates for encoder and registers. The high speed flash ADC is simulated in a 1P6M 180nm CMOS process with 1-V supply voltage and consumes 0.432-mW. At 50 MS/s, high speed flash ADC has the effective number of bits of 5.95-bit and the figure of merit of 0.15 pJ/conversion-step effective no of bit is 5.95, signal to noise distortion ratio is 37.60 db and SFDR is 45.4 db.