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Design of Two Stage CMOS Operational Amplifier
Journal: International Journal of Science and Research (IJSR) (Vol.10, No. 6)Publication Date: 2021-06-05
Authors : Rahul Kumar;
Page : 1505-1508
Keywords : CMOS op-amp design; frequency response; noise; simulation;
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Abstract
This paper presents a design of two stage CMOS operational amplifier, which operates at +1.8V and -1.8V power supply using 180nm CMOS technology. The op-amp designed is a two stage CMOS op-amp. The op-amp is designed to exhibit a gain bandwidth of 30 MHz and exhibits a gain of 68.74dB with a 179.94 phase margin. Design and simulation has been carried out in LTSPICE tool.
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Last modified: 2021-07-05 13:46:22