A Novel Approach for Auto Clock Gating of Flip-Flops

Clock gating is a one of the power saving technique. It is a popular technique used in many synchronous circuits for reducing dynamic power dissipation and extraordinarily helpful for decreasing the ability power wasted by digital circuits. This paper proposes a new technique of look ahead clock gating. It avoids and replaces the drawbacks of the previously existing ways. the present systems for clock gating are synthesis base clock gating, information driven clock gating and clock gating on auto gated flip flops however of these techniques had some disadvantages. This project deals with the replaces the drawbacks within the existing system Look-Ahead Clock Gating (LACG), combines all the three. LACG computes the clock enabling signals of every FF one cycle before time, supported the current cycle information of these FFs on that it depends. It avoids the tight temporal arrangement constraints of AGFF and data-driven by allotting a full clock cycle for the computation of the enabling signals and their propagation. The Simulation will be done in Tanner EDA 13.0v T-Spice at 0.18um