Design and Implementation of Four Bit Binary Array Multiplier

Recently, several experimental systems based on programmable logic have been designed and implemented which are programmed using a hardware design methodology. One necessary component of the software environment will be a library of standard macro cells corresponding to commonly used arithmetic and logical operations. In this paper Array multiplier is designed especially for programmable logic. This multiplier is cellular, highly pipelined and uses only of local interconnections. The design is particularly carried out for a 4- bit multiplier.