Implementation of AES Using Reversible Cellularautomata Based S-Box on FPGA

The paper presents an efficient reconfigurable hardware implementation of Advance Encryption Standard(AES) algorithm on Field Programmable Gate Array (FPGA); using High Level Language (HLL) approach with lesser hardware resources. The mode of data transmission in the modified AES is 128-bit plaintext and keys which converted into four 32bit blocks and exclusion of shift row. Using this feature, not only area is optimized but also higher throughput is achieved.The proposed architecture can deliver higher throughput at both encryption and decryption operations. Design has been done using Verilog and simulated using ModelSim. The design has been synthesized using Xilinx 14.5 for target device Spartan6