Application of 6:2 Compressor in the Design of Multiplier

Multiplier is the key element in the digital and high performance systems like FIR filters, processors and controllers. Multipliers are complex units and play an important role in deciding the overall area, speed and power consumption of digital circuit design. Hence, the design of multiplier must utilise the less number of transistors. Full adder is used to design such multiplier. Here the utilisation of number of adders has been reduced by introducing different compressor methods. The result achieved with 40% reduction in area, 05% reduction in power, 45% reduction in delay and 40% reduction in number of transistors.