Skew Reduction Technique Using the Clock Mesh Analysis in DDR IP Structural Design Development for Server Products

As the technology node decreases timing closure has become the major bottleneck in the physical designs. Backend designers are expected to meet the clock frequency specified by the top level system architects instead of growing the size and timing convergence complexities of today?s backend designs. One of the main convergence complexities of today?s design is the process variation. Earlier method like clock tree synthesis is used to reduce the skew for slow processor clocks. Clock tree mesh (CT mesh) is used for the higher end processes. Clock tree synthesis is not resistant to On Chip Variation (OCV) but the clock mesh is resistant to OCV and yields the higher performance. The OCV can also be removed by using the guard banding, but by doing so we need to compromise the performance. This is the reason for performing clock mesh analysis. In this paper we have mainly concentrated on the reduction of the global skew and the local skew.