Design of Efficient Braun Multiplier for Arithmetic Applications

Multiplier plays key role in Digital Signal Processing and FPGA based applications, as it consumes more power and area compared other devices. In DSP and FPGA based applications power, speed and area all are important parameters and all depend on multiplier which in turn depends on adders. So, by implementing adders we can reduce the delay. Pyramidal adders are used which uses half-adder and full-adder to increase the speed and to reduce the number of gates used in the multiplier, but delay is not decreased significantly. If we modify the Pyramidal adder with XNOR?s and MUX instead of normal half-adder and full-adder, such pyramidal adder uses less gates and delay is reduced compared normal 16-bit adder. The use of XNOR?s and MUX in Pyramidal adder reduces delay, as the MUX function is only select the output among inputs. The use such pyramidal adder in multiplier delay can be decreased greatly. Modified full adder sum and carry values are same as normal full adder but the transistor topology is different.