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Interfacing BLE Module on FPGA using Nios II

Journal: International Journal of Science and Research (IJSR) (Vol.10, No. 8)

Publication Date:

Authors : ; ;

Page : 1020-1022

Keywords : Nios II Processor; BLE; UART;

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This paper presents the implementation of Bluetooth Low Energy (BLE) on Field Programmable Gate Array (FPGA) using System on Programmable chip (SOPC). The design is implemented using the soft intellectual property (IPs) of the Nios II processor. The test results are verified on the serial terminal. This implementation has applications in the designing of wireless gateway on FPGA.

Last modified: 2022-02-15 18:36:48