IMPROVED ARCHITECTURE ON 32-POINT RADIX-4 FAST FOURIER TRANSFORM WITH VEDIC MULTIPLIER

In the action of arithmetic logic, abstract multiplication is an important feature. The computer efficiency is constrained by its performance multiplication, which limits the execution time of digital signal processing algorithms. The aim of our project is to develop the FFT-4 radix Vedic multiplier VLSI based adaptive architecture. There are more internal Gate Circuit complexity levels in the parallel multiplier architecture. Thus, we refine the parallel multiplier design level and apply the Vedic architecture multiplier for continuous multiplication. This design reduces the complexity, strength and speed of the FFT architecture faster than parallel multipliers.